1. Field of the Invention
The present invention relates, in general, to semiconductor structures and, more particularly, to bipolar or BiCMOS device fabrication on SOI substrates.
2. Background of the Invention
A fundamental requirement of device integration in silicon is the electrical isolation of devices. Resistances and capacitances associated with possible isolation schemes must be held to a minimum in order sacrifice the device performance as little as possible.
In light of these integration principles, device fabrication on silicon-on-insulator (SOI) substrates offers distinct advantages (in particular for CMOS devices) if the SOI film is sufficiently thin so that the source/drain junctions are butted to the buried oxide of the SOI.
The conventional structure of a bipolar transistor, in comparison, would require a significantly thicker SOI film due to the vertical current flow and the relatively thick subcollector contact. These diverging requirements on the SOI-film thickness make the combined integration of CMOS and vertical bipolar transistors, as needed for an SOI BiCMOS technology, very difficult.
One way to fabricate bipolar transistors in thin-SOI films is to design the transistor as a lateral device similar to the CMOS. Such a device has been demonstrated in recent years, such as in the paper by G. Shahidi et al., Tech. Digest IEDM 1991, pp.663-666, and the paper by R. Dekker et al., Techn. Digest IEDM 1993, pp.75-78. The formation of a thin base region in a lateral bipolar transistor structure is a difficult task, which is the reason that for this device type a cutoff-frequency of only .congruent.15 GHz has been demonstrated to date. Also, the formation of an epitaxial Si or SiGe-base, which would provide a high cutoff frequency, in a lateral transistor is extremely difficult, and no results for such a structure have been published yet. A structural concept of a lateral SiGe-HBT has been published by B. Davari et al., IBM Techn. Discl. Bulletin, vol. 36, no. 4, 1993, p.139, but without successful reduction to practice.
It can be said in general, that very high intrinsic device speed requires the formation of a vertical emitter-base junction of the transistor, and preferably with a SiGe-base which is epitaxially grown. In light of the previous explanations, it would be desirable to build a bipolar transistor on a thin-SOI substrate such that the emitter-base junction is grown epitaxially and formed vertically, that the collector contact is attached laterally without a subcollector, and that the device has a single base contact opposite the collector contact. Such a structure, fabricated in bulk-silicon, has been proposed by Iyer et al in U.S. Pat. No. 4,738,624. The motivation for that device structure was to skip the trench formation which is usually needed to isolate integrated bipolar transistors. Another device structure, which meets some of the criteria listed above, is described in the U.S. Pat. No. 5,087,580 by R. Eklund. This proposal does not consider epitaxial Si or SiGe base formation and uses a non-self-aligned, non-walled emitter. The bipolar transistor by Eklund integrates well with CMOS on SOI, but the transistor performance is limited by considerable contact resistances of collector and base and by not considering an epitaxial Si or SiGe base region. Neither patent, however, describes a solution to the problem associated with making a transistor suitable for high-performance device operation.
It is clear from the above explanations and the discussion of the prior art that it would be desirable to provide a bipolar transistor structure which combines the various attributes addressed above.